{"id":668,"date":"2021-12-21T15:17:00","date_gmt":"2021-12-21T07:17:00","guid":{"rendered":"https:\/\/ecmos2.liho.work\/?p=668"},"modified":"2024-09-10T13:41:07","modified_gmt":"2024-09-10T05:41:07","slug":"ec25c32","status":"publish","type":"post","link":"https:\/\/www.ecmos.com.tw\/cn\/eeprom\/ec25c32\/","title":{"rendered":"EC25C32\uff5c32Kbits SPI Serial EEPROM"},"content":{"rendered":"\n
\u898f\u683c\u66f8\u4e0b\u8f09<\/div><\/a>\n\n\n\n
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General description<\/h3>\n\n\n\n

The EC25C32 is an industrial standard electrically erasable programmable read only memory (EEPROM) Product that utilizes standard Serial Peripheral Interface (SPI) for communications. The EC25C32 contains a memory array of 32K bits (4,096x 8), which is organized in 32 bytes per page.
This EEPROM operates in a wide voltage range from 1.7V to 5.5V,which fits most application. The device provides low-power operations and low standby current. The product is offered in Lead-free, RoHS, halogen free or Green package. The available package types are 8-pin SOP,<\/p>\n\n\n\n

TSSOP and UDFN.<\/p>\n\n\n\n

The functionalities of the EC25C32 are optimized for most applications, such as consumer electronics,wireless,telecommunication, industrial, medical ,instrumentation, commercial and others, where low-power and low-voltage<\/p>\n\n\n\n

Are vital. This product has a compatible SPI interface: Chip-Select ( CS ), Serial Data In (SI), Serial Data Out (SO) and Serial Clock (SCK) for high-speed communication. Furthermore, a Hold feature via HOLD pin allows the device entering into a suspended state whenever necessary and resuming the communication without re-initializing the serial sequence. A Status Register facilitates a flexible write protection mechanism and deviceStatus monitoring.<\/p>\n\n\n\n

In order to refrain the state machine from entering into a
Wrong state during power-up sequence or a power toggle off-on condition, a power on reset circuit is implemented. During power-up, the device does not respond to any instructions until the supply voltage (VCC)has reached an acceptable stable level above the reset threshold voltage. Once VCC passes the power on reset threshold, the device is reset and enters into Standby mode. This should also avoid any inadvertent Write operations during power-up stage. During power-down process, the device will enter into standby mode, once VCC drops below the power on reset threshold voltage. In addition, the device will be in standby mode after receiving the Stop command, provided that no internal write operation is in progress. Nevertheless,<\/p>\n\n\n\n

it is illegal to send a command unless the VCC is within its operating level.<\/p>\n\n\n\n

Features<\/h3>\n\n\n\n

\u00b7Serial Peripheral Interface (SPI) Compatible
\u2014Supports Mode 0 (0,0) and Mode 3 (1,1)<\/p>\n\n\n\n

\u00b7Wide-voltage Operation<\/p>\n\n\n\n

\u2014VCC = 1.7V to 5.5V<\/p>\n\n\n\n

\u00b7Low power CMOS<\/p>\n\n\n\n

\u2014Standby current: \u22641 \u03bcA (1.7V)<\/p>\n\n\n\n

\u2014Operating current: \u22641 mA (1.7V)<\/p>\n\n\n\n

\u00b7Operating frequency: 20 MHz (5.5V)<\/p>\n\n\n\n

\u00b7Memory organization: 32Kb (4,096 x 8)<\/p>\n\n\n\n

\u00b7Byte and Page write (up to 32 bytes)<\/p>\n\n\n\n

\u2014Partial page write allowed<\/p>\n\n\n\n

\u00b7 Block Write Protection
\u2014 Protect 1\/4, 1\/2, or Entire Array<\/p>\n\n\n\n

\u00b7 Self timed write cycle: 5 ms (max.)<\/p>\n\n\n\n

\u00b7 Additional Write lockable Page (Identification<\/p>\n\n\n\n

page)<\/p>\n\n\n\n

\u00b7 High-reliability<\/p>\n\n\n\n

\u2014 Endurance: 1 million cycles<\/p>\n\n\n\n

\u2014 Data retention: 100 years<\/p>\n\n\n\n

\u00b7 Industrial temperature grade<\/p>\n\n\n\n

\u00b7 Packages (8-pin): SOP, TSSOP and DFN<\/p>\n\n\n\n

\u00b7 Lead-free, RoHS, Halogen free, Green<\/p>\n\n\n\n

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