EC24CXXT|2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM

EC24CXXT|2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM


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2K/4K/8K/16K-bit​​ 2-WIRE SERIAL CMOS EEPROM

EC24CXXT

 

 

Features

Wide Voltage Operation​​ - VCC = 1.8V to 5.5V

Operating Ambient Temperature: -40​​ to +85

Internally Organized:

-​​ EC24C02T, 256 X 8 (2K bits)

-​​ EC24C04T, 512 X 8 (4K bits)

-​​ EC24C08T, 1024 X 8 (8K bits)

-​​ EC24C16T, 2048 X 8 (16K bits)

Two-wire Serial Interface

Schmitt Trigger, Filtered Inputs for Noise Suppression

Bidirectional Data Transfer Protocol

1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility

Write Protect Pin for Hardware Data Protection

8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes

Partial Page Writes Allowed

Self-timed Write Cycle (5 ms max)

High-reliability​​ 

- Endurance: 1 Million Write Cycles

- Data Retention: 100 Years

DIP8, SOP8TSSOP8MSOP8​​ and​​ SOT23-5​​ Packages

Die Sales: Wafer Form, Waffle Pack

 

General Description

The​​ EC24C02T/EC24C04T/EC24C08T/EC24C16T​​ provides 2048/4096/8192/16384 bits of serial​​ electrically erasable and programmable read-only memory (EEPROM) organized as​​ 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and​​ commercial applications where low-power and low-voltage operations are essential. The​​ EC24C02T/EC24C04T/EC24C08T/EC24C16T​​ is available in space-saving DIP8, SOP8, TSSOP8,​​ MSOP8,

and​​ SOT23-5​​ packages and is accessed via a two-wire serial interface.

 

Pin Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TSSOP-8

 

 

 

 

 

 

Pin Descriptions

Table 1

Pin Designation

Type

Name and Functions

A0 - A2

I

Address Inputs

SDA

I/O & Open-drain

Serial Data

SCL

I

Serial Clock Input

WP

I

Write Protect

GND

P

Ground

VCC

P

Power Supply

NC

NC

No Connect

 

Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Descriptions

DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs​​ that are hard wired for the​​ EC24C02T. Eight 2K devices may be addressed on a single bus system​​ (device addressing is discussed in detail under the Device Addressing section).​​ The​​ EC24C04T​​ uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may​​ be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.

The​​ EC24C08T​​ only uses the A2 input for hardwire addressing and a total of two 8K devices may be​​ addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to​​ ground.

The​​ EC24C16T​​ does not use the device address pins, which limits the number of devices on a single​​ bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground.​​ SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain​​ driven and may be wire-ORed with any number of other open-drain or open- collector devices.

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM​​ device and negative edge clock data out of each device.

WRITE PROTECT (WP): The​​ EC24C02T/EC24C04T/EC24C08T/EC24C16T​​ has a Write Protect pin​​ that provides hardware data protection. The Write Protect pin allows normal read/write operations​​ when connected to ground (GND). When the Write Protect pin is connected to VCC, the write​​ protection feature is enabled and operates as shown in the following Table 2.

 

WP Pin Status

Part of the Array Protected

EC24C02T

EC24C04T

EC24C08T

EC24C16T

At VCC

Full (2K) Array

Full (4K) Array

Full (8K) Array

Full (16K) Array

At GND

Normal Read/Write Operations

 

Memory Organization

EC24C02T, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K​​ requires an 8-bit data word address for random word addressing.

EC24C04T, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K​​ requires a 9-bit data word address for random word addressing.

EC24C08T, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K​​ requires a 10-bit data word address for random word addressing.

EC24C16T, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K​​ requires an 11-bit data word address for random word addressing.

 

Device Operation

CLOCK and DATA TRANSITIONS

The SDA pin is normally pulled high with an external device.​​ Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 5). Data​​ changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION

A high-to-low transition of SDA with SCL high is a start condition which​​ must precede any other command (see to Figure 2 on page 5).

STOP CONDITION

A low-to-high transition of SDA with SCL high is a stop condition. After a​​ read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on​​ page 5).

 

 

 

ACKNOWLEDGE

All addresses and data words are serially transmitted to and from the EEPROM​​ in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This​​ happens during the ninth clock cycle.

STANDBY MODE

The​​ EC24C02T/EC24C04T/EC24C08T/EC24C16T​​ features a low-power standby​​ mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the​​ completion of any internal operations.

MEMORY RESET

After an interruption in protocol, power loss or system reset, any two-wire part​​ can be reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

 

Figure 1: Data Validity

 

 

 

 

 

 

 

 

Figure 2: Start and Stop Definition

 

 

 

 

 

 

 

 

 

Figure 3: Output Acknowledge

 

 

 

 

 

 

 

 

 

 

 

 

 

Device Addressing

The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start​​ condition to enable the chip for a read or write operation (see to Figure 4 on page 8).​​ The device address word consists of a mandatory "1", "0" sequence for the first four most significant​​ bits as shown. This is common to all the Serial EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must​​ compare to their corresponding hardwired input pins.​​ The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page​​ address bit. The two device address bits must compare to their corresponding hardwired input pins.

The A0 pin is no connect.​​ The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page​​ addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins​​ are no connect.

The 16K does not use any device address bits but instead the 3 bits are used for memory page​​ addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most​​ significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect.​​ The eighth bit of the device address is the read/write operation select bit. A read operation is initiated​​ if this bit is high and a write operation is initiated if this bit is low.​​ Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the​​ chip will return to a standby state.

 

Write Operations

BYTE WRITE

A write operation requires an 8-bit data word address following the device address​​ word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0"​​ and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will​​ output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence​​ with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the​​ nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond​​ until the write is complete (see Figure 5 on page 7).

PAGE WRITE

The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K​​ devices are capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop​​ condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of​​ the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more​​ data words. The EEPROM will respond with a "0" after each data word received. The microcontroller​​ must terminate the page write sequence with a stop condition (see Figure 6 on page 8).

The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented​​ following the receipt of each data word. The higher data word address bits are not incremented,​​ retaining the memory page row location. When the word address, internally generated, reaches the​​ page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K)​​ or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll​​ over" and previous data will be overwritten.

ACKNOWLEDGE POLLING

Once the internally timed write cycle has started and the EEPROM​​ inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition​​ followed by the device address word. The read/write bit is representative of the operation desired.​​ Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read​​ or write sequence to continue.

 

Read Operations

Read operations are initiated the same way as write operations with the exception that the read/write​​ select bit in the device address word is set to "1". There are three read operations: current address read,​​ random address read and sequential read.

 

 

 

 

CURRENT ADDRESS READ

The internal data word address counter maintains the last address​​ accessed during the last read or write operation, incremented by one. This address stays valid between​​ operations as long as the chip power is maintained. The address "roll over" during read is from the last​​ byte of the last memory page to the first byte of the first page. The address "roll over" during write is​​ from the last byte of the current page to the first byte of the same page.​​ Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the​​ EEPROM, the current address data word is serially clocked out. The microcontroller does not respond​​ with an input "0" but does generate a following stop condition (see Figure 7 on page 8).

RANDOM READ

A random read requires a "dummy" byte write sequence to load in the data word​​ address. Once the device address word and data word address are clocked in and acknowledged by the​​ EEPROM, the microcontroller must generate another start condition. The microcontroller now​​ initiates a current address read by sending a device address with the read/write select bit high. The​​ EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller

does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 9).

SEQUENTIAL READ

Sequential reads are initiated by either a current address read or a random​​ address read. After the microcontroller receives a data word, it responds with an acknowledge. As​​ long as the EEPROM receives an acknowledge, it will continue to increment the data word address​​ and serially clock out sequential data words. When the memory address limit is reached, the data word​​ address will "roll over" and the sequential read will continue. The sequential read operation is

terminated when the microcontroller does not respond with a "0" but does generate a following stop​​ condition (see Figure 9 on page 9).

 

Figure 4: Device Address

 

 

 

 

 

 

 

Figure 5: Byte Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6: Page Write

 

 

 

 

 

 

 

 

Figure 7: Current Address Read

 

 

 

 

 

 

 

 

Figure 8: Random Read