{"id":661,"date":"2020-04-26T15:12:56","date_gmt":"2020-04-26T07:12:56","guid":{"rendered":"https:\/\/ecmos2.liho.work\/?p=661"},"modified":"2024-09-10T13:45:22","modified_gmt":"2024-09-10T05:45:22","slug":"ec93c56a_66a","status":"publish","type":"post","link":"https:\/\/www.ecmos.com.tw\/en\/eeprom\/ec93c56a_66a\/","title":{"rendered":"EC93C56A\/66A\uff5cThree-Wire Serial EEPROM"},"content":{"rendered":"\n
\u898f\u683c\u66f8\u4e0b\u8f09<\/div><\/a>\n\n\n\n
\n\n\n\n

General description<\/h3>\n\n\n\n

The EC93C56A\/66A provides 2048\/4096 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 128\/256 words of 16 bits each, when the ORG pin is connected to VCC and 256\/512 words of 8 bits each when it is tied to ground.<\/p>\n\n\n\n

The EC93C56A\/66A is available in space-saving PDIP-8, SOP-8, TSSOP-8, MSOP-8, and DFN-8 packages.<\/p>\n\n\n\n

The EC93C56A\/66A is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK).<\/p>\n\n\n\n

Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate erase cycle is required before write.<\/p>\n\n\n\n

The Write cycle is only enabled when it is in the Erase\/Write Enable state. When CS is brought \u201chigh\u201d following the initiation of a write cycle, the DO pin outputs the Ready\/Busy status.<\/p>\n\n\n\n

Features<\/h3>\n\n\n\n

\u25c6Low-voltage Operation -1.7V (VCC = 1.7V to 5.5V)
\u25c6 Three-wire Serial Interface
\u25c6 Sequential Read Operation
\u25c6 2 MHz Clock Rate (5V) Compatibility
\u25c6 Self-timed Write Cycle (5 ms max)
\u25c6 High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
\u25c6 PDIP-8, SOP-8, TSSOP-8, MSOP-8 and DFN-8 packages.<\/p>\n\n\n\n

\n\n\n\n