2A Sink/Source Bus Termination Regulator
EC9175
General Description
The EC9175 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage
in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific
interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively
sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab
be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can
be programmed by externally forcing the REFEN pin voltage.
The EC9175 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient.
Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions
and on-chip thermal shut-down protection. The EC9175 are available in the ESOP8 (Exposed Pad) surface mount
packages.
Features
◆Ideal for DDR-I, DDR-II and DDR-III VTT Applications
◆Sink and Source 2A Continuous Current
◆Integrated Power MOSFETs
◆Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces.
◆High Accuracy Output Voltage at Full-Load
◆Output Voltage traces REFEN Pin Voltage.
◆Low External Component Count
◆Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output
◆Current Limiting Protection
◆Thermal Shutdown Protection
◆ESOP-8 with exposed pad Pb-Free Package.
Applications
◆Desktop PCs, Notebooks, and Workstations
◆Graphics Card Memory Termination
◆Set Top Boxes, Digital TVs, Printers
◆Embedded Systems
◆Active Termination Buses
◆DDR-I, DDR-II and DDR-III Memory Systems
Typical application
Ordering/Marking Information
EC9175 XX X X
R：Tape & Reel
Package Type： F：Pb Free
MH：ESOP8 G：Green
Device | Marking | Package | Information |
EC9175MHXR | EC9175 LLLLL YYWW | ESOP8 | YY: Year code WW: Week code LLLLL: Lot no. |
Pin Configurations
Pin Description
NO. | Pin Name | Pin Function Description |
1 | VIN | Input Voltage pin |
2 | GND | Ground pin |
3 | REFEN | Reference voltage input and chip enable pin |
4 | VOUT | Output Voltage pin |
5,7,8 | NC | No connect pin |
6 | VCNTL | Supply Input and Gate drive voltage pin |
Functional Block Diagram
Absolute Maximum Ratings
Symbol | Parameter | Maximum | Units |
VIN | VIN Supply Voltage | 6 | V |
VCNTL | Control Voltage | 6 | V |
PD | Power Dissipation | Internally Limited | W |
TST | Storage Temperature Range | -40 to +150 | ℃ |
θJC | Thermal Resistance from Junction to case | 15 | ℃/W |
θJA | Thermal Resistance from Junction to ambient | 40 | ℃/W |
Note:
θJA is measured with the PCB copper area (need connect to Exposed pad) of approximately in1.5 2
Recommended Operating Conditions
Symbol | Parameter | Maximum | Units |
VIN | Input Voltage | 1.3 to VCNTL | V |
VCNTL | Control Voltage | 5 or 3.3 | V |
TA | Ambient Temperature | -40 to +85 | ℃ |
TJ | Junction Temperature | -40 to +125 | ℃ |
Note:
VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Electrical Characteristics
（VIN=2.5V/1.8V/1.5V, VCNTL=3.3V, VREFEN=1.25V/0.9V/0.75V, COUT=10μF (Ceramic),；Tj=25℃ unless
otherwise specified）
Symbol | Parameter | Test Conditions | Min | Typ | Max | Unit |
VCNTL | Gate Drive Voltage Range |
| - | 3.3 | 5.5 | V |
VCNTLRTH | POR Threshold |
| - | 2.55 | - | V |
VCNTL | POR Hysteresis |
| - | 0.1 | - | V |
VIN | Input Voltage |
| 1.3 | - | VCNTL | V |
ICNTL | Quiescent Current | IOUT=0A | - | 1 | 3 | mA |
ISTBY | Standby Current | IOUT=0A, VREFEN=0V | - | 1 | 10 | uA |
VOS | Output Offset Voltage (Note1) | IOUT=0A | -20 | - | +20 | mV |
△VLOAD | Load Regulation (Note2) | IOUT=±2.0A | - | 0.5 | ±20 | % |
VIH | Shutdown Threshold | Enable, REFEN Rising | 0.65 | - | - | V |
VIL | Shutdown, REFEN Falling | - | - | 0.2 | V | |
ICL-Source | Current Limit | Sourcing | 2.1 | - | - | A |
ICL-Sink | Sinking | 2.1 | - | - | A | |
TSS | Soft-Start Period | VOUT=1.25V | - | 1.4 | - | ms |
TSD | Thermal Shutdown |
| - | 155 | - | ℃ |
TSDH | Thermal Shutdown Hysteresis |
| - | 30 | - | ℃ |
Note 1: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 2: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested
for load regulation in the load range from 0A to 2A.
Typical Performance Characteristics
Transient Test
Typical Performance Characteristics（continuous）
Soft-Start