-- 1.8 (VCC = 1.8V to 5.5V)
Operating Ambient Temperature: -40°C to +85°C
Internally Organized 65,536 X 8 (512K)
Two-wire Serial Inter
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1MHZ(5V),400 kHz (1.8V, 2.5V, 2.7V)
Write Protect Pin for Hardware Data Protection
128-byte Page (512K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
-- Endurance: 1 Million Write Cycles
-- Data Retention: 100 Years
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
The EC24C512T provides 524,28 bits of serial electrically erasable and programmable read only memory (EEPROM)) organized as 65,536 words of 8bits each. The device’s cascadable features allows up to eight devices to share a common two-wire bus.
The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP.
Table1: Pin Configuration
Name and Function
I/O & Open-Drain
Serial Clock Input
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other EC24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Fs-Rank recommends always connecting the address pins to a known state. When using a pull-up resistor, Fs-Rank recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Fs-Rank recommends always connecting the WP pins to a known state. When using a pull-up resistor, Fs-Rank recommends using 10kΩ or less.
Table 2: Write Protect
WP Pin Status
Part of the Array Protected
Full (512k) Array
Normal Read/Write Operations
EC24C512T, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128 bytes each. Random word addressing requires a 16-bit data word address
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command.
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby mode.
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle
STANDBY MODE: The EC24C512T features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:
Clock up to 9 cycle
Look for SDA high in each cycle while SCL is high.
Create a start condition.
Figure 1. Data Validity
Figure 2. Start and Stop Definition
Figure 3. Output Acknowledge