EC24C128T|128-Kbit I 2 C-compatible Serial EEPROM

EC24C128T|128-Kbit I 2 C-compatible Serial EEPROM


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128-Kbit I​​ 2​​ C-compatible Serial EEPROM

EC24C128T

 

 

Features

 

  • Supply Voltage: 1.7V to 5.5V

  • 2-wire Serial Interface I​​ 2​​ C Compatible

----​​ 400 kHz and High Speed 1MHz Transfer Rate Compatibility

  • Byte and Page (up to 64 Bytes) Write Mode

----​​ Partial Page Writes Allowed

  • Self-timed Write Cycle (5ms Maximum)

  • Hardware Write Protection on the Whole Memory Array

  • Additional 64-byte Write Lockable Page and 128-bit Unique ID

  • Schmitt Trigger, Filtered Inputs for Noise Suppression

  • High Reliability

----​​ Endurance: 1,000,000 Write Cycles

----​​ Data Retention: 100 Years

  • Low Operating Current

----​​ Write Current: 1mA (Maximum)

----​​ Read Current: 0.5mA (Maximum)

----​​ Standby Current: 1μA (Maximum)

  • Operating Temperature Range: -40°C to +105°C

  • Green Packaging Options​​ 

----​​ TSSOP-8, SOP-8,​​ SOT23-5

 

 

 

Description​​ ​​ 

The​​ EC24C128T​​ is a 128-Kbit I​​ 2​​ C-compatible Serial EEPROM (Electrically Erasable Programmable Memory) device. The device is designed to operate in a supply voltage range of 1.7V to 5.5V, with a maximum of 1MHz transfer rate. The operating temperature range is from -40°C to +105°C. The device incorporates a Write Protection pin used for hardware Write Protection on the whole memory array.

The Serial EEPROM memory is organized as 256 pages of 64 bytes each, totaling 16384*8 bits. The EC24C128T offers an additional 64-byte Identification Page for users to store sensitive application parameters. This page can be permanently locked in Read-only mode after the application data is written into the Identification Page. The​​ EC24C128T also offers a separate memory block containing a factory programmed 128-bit Unique ID. This block is in Read-only mode and can be accessed to by sending a specific Read command

The EC24C128T is delivered in Lead-free green packages: TSSOP-8, SOP-8, SOT23-5

 

 

 

 

 

 

 

 

 

  • Pin Descriptions and Pin Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 Functional Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 Device Communication

The EC24C128T operates as a slave device and utilizes a 2-wire serial interface to communicate with the Master. The Master initiates and controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: the Serial Clock (SCL) and the Serial Data (SDA). Data is always latched into the​​ EC24C128T​​ on the rising edge of SCL and is always output from the device on the falling edge of SCL. Both the SCL pin and SDA pin incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus noise.

All command and data information is transferred with the Most Significant Bit (MSB) first. During the bus communication, one data bit is transmitted every clock cycle, and after eight bits of data has been transferred, the receiving device must respond with an acknowledge or a no-acknowledge response bit during a ninth clock cycle generated by the Master. Therefore, nine clock cycles are required for every one byte of data transferred. There is no unused clock cycle during any Read or Write operation, so there must not be any interruptions or breaks during the data stream.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. The number of data bytes transferred between a Start and a Stop condition is not limited and is determined by the Master.

 

 

 

3.1 Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is stable in Logic 1 state. The Start condition must precede any command as the Master uses a Start condition to initiate any data transfer sequence (see Figure 3–1). The​​ EC24C128T​​ will continuously monitor the SDA and SCL pins for a Start condition, and the device will not respond unless one is given.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.2 Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in Logic 1 state (see Figure 3–1). A stop condition terminates communication between the​​ EC24C128T​​ and the Master. A Stop condition at the end of a Write command triggers the EEPROM internal write cycle. Otherwise, the​​ EC24C128T​​ subsequently returns to Standby mode after receiving a Stop condition.

 

 

3.3 Acknowledge (ACK)

After each byte of data is received, the​​ EC24C128T​​ should acknowledge to the Master that it has received the data byte successfully. This is accomplished by the Master first releasing the SDA line and providing the ACK/NACK clock cycle (a ninth clock cycle for every byte). During the ACK/NACK clock cycle, the​​ EC24C128T​​ must output Logic 0 as ACK for the entire clock cycle so that the SDA line must be stable in Logic 0 state during the entire high period of the clock cycle (see Figure 3–1).

 

 

3.4 Standby Mode

The​​ EC24C128T​​ features a low-power Standby mode which is enabled:​​ 

(1) Upon power-up;​​ 

(2) After the receipt of a Stop condition in Read operation;

(3) The completion of any internal operations.

 

 

3.5 Software Reset

After an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by following these steps: (1) Create a Start condition; (2) Clock nine cycles; (3) Create another Start condition followed by a Stop condition (see Figure 3–2).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.6 Device Reset and Initialization

The​​ EC24C128T​​ incorporates a Power-On Reset (POR) circuit to prevent inadvertent operations during power-up. On a cold power-up, the device does not respond to any instructions until the supply voltage reaches the internal power-on reset threshold voltage (VPOR). The supply voltage must rise continuously between VPOR​​ and VCC(Min) without any ring back to ensure a proper power-up. Once the supply voltage passes VPOR, the device is reset and enters Standby mode. However, no protocol should be issued to the device until a valid and stable supply voltage is applied for the time specified by the tINIT​​ parameter. The supply voltage must remain stable and valid until the end of the protocol transmission, and for a Write instruction, until the end of the internal write cycle (see Figure 3–3).

This POR behavior is bi-directional. It protects the​​ EC24C128T​​ against brown-out failure caused by a temporary loss of power. In a similar way, as soon as the supply voltage drops below the internal brown-out reset threshold voltage (VBOR), the device is reset and stops responding to any instructions (see Figure 3–3). The VBOR​​ level is set below the VPOR​​ level.

Parameters related to power-up and power-down conditions are listed in Table 3–1.